INSULATED GATE BIPOLAR TRANSISTOR (IGBT)

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The Insulated Gate Bipolar Transistor (IGBT) is a minority-carrier device with high input impedance and large bipolar current-carrying capability. Many designers view IGBT as a device with MOS input characteristics and bipolar output characteristic that is a voltage-controlled bipolar device. To make use of the advantages of both Power MOSFET and BJT, the IGBT has been introduced. It’s a functional integration of Power MOSFET and BJT devices in monolithic form. It combines the best attributes of both to achieve optimal device characteristics

The IGBT is suitable for many applications in power electronics, especially in Pulse Width Modulated (PWM) servo and three-phase drives requiring high dynamic range control and low noise. It also can be used in Uninterruptible Power Supplies (UPS), Switched-Mode Power Supplies (SMPS), and other power circuits requiring high switch repetition rates. IGBT improves dynamic performance and efficiency and reduced the level of audible noise. It is equally suitable in resonant-mode converter circuits. Optimized IGBT is available for both low conduction loss and low switching loss.

main advantages of IGBT over a Power MOSFET and a BJT are:

1. It has a very low on-state voltage drop due to conductivity modulation and has superior on-state current density. So smaller chip size is possible and the cost can be reduced.

2. Low driving power and a simple drive circuit due to the input MOS gate structure. It canbe easily controlled as compared to current controlled devices (thyristor, BJT) in high voltage and high current applications.

3. Wide SOA. It has superior current conduction capability compared with the bipolar transistor. It also has excellent forward and reverse blocking capabilities.

The main drawbacks are:

1. Switching speed is inferior to that of a Power MOSFET and superior to that of a BJT. The collector current tailing due to the minority carrier causes the turnoff speed to be slow

2. There is a possibility of latchup due to the internal PNPN thyristor structure

The IGBT is suitable for scaling up the blocking voltage capability. In case of Power MOSFET, the on-resistance increases sharply with the breakdown voltage due to an increase in the resistively and thickness of the drift region required to support the high operating voltage. For this reason, the development of high current Power MOSFET with high-blocking voltage rating is normally avoided. In contrast, for the IGBT, the drift region resistance is drastically reduced by the high concentration of injected minority carriers during on-state current conduction. The forward drop from the drift region becomes dependent upon its thickness and independent of its original resistivity.

Basic Structure

The basic schematic of a typical N-channel IGBT based upon the DMOS process is This is one of several structures possible for this device. It is evident that the silicon cross-section of an IGBT is almost identical to that of a vertical Power MOSFET except for the P+ injecting layer. It shares similar MOS gate structure and P wells with N+ source regions. The N+ layer at the top is the source or emitter and the P+ layer at the bottom is the drain or collector. It is also feasible to make P-channel IGBTs and for which the doping profile in each layer will be reversed. IGBT has a parasitic thyristor comprising the four-layer NPNP structure. Turn-on of this thyristor is undesirable.

Some IGBTs, manufactured without the N+ buffer layer, are called non-punch through(NPT) IGBTs whereas those with this layer are called punch-through (PT) IGBTs. The presence of this buffer layer can significantly improve the performance of the device if the doping level and thickness of this layer are chosen appropriately. Despite physical similarities, the operation of an IGBT is closer to that of a power BJT than a power MOSFET. It is due to the P+ drain layer (injecting layer) which is responsible for the minority carrier injection into the N--drift region and the resulting conductivity modulation.

Based on the structure, a simple equivalent circuit model of an IGBT can be drawn as It contains MOSFET, JFET, NPN and PNP transistors. The collector of the PNP is connected to the base of the NPN and the collector of the NPN is connected to the base of the PNP through the JFET. The NPN and PNP transistors represent the parasitic thyristor which constitutes a regenerative feedback loop. The resistor RB represents the shorting of the base-emitter of the NPN transistor to ensure that the thyristor does not latch up, which will lead to the IGBT latchup. The JFET represents the constriction of current between any two neighboring IGBT cells. It supports most of the voltage and allows the MOSFET to be a low voltage type and consequently have a low RDS(on) value. A circuit symbol for the IGBT It has three terminals called Collector (C), Gate (G) and Emitter (E).

IXYS has developed both NPT and PT IGBTs. The physical constructions for both of them are As mentioned earlier, the PT structure has an extra buffer layer which performs two main functions: (i) avoids failure by punch-through action because the depletion region expansion at applied high voltage is restricted by this layer, (ii) reduces the tail current during turn-off and shortens the fall time of the IGBT because the holes are injected by the P+ collector partially recombine in this layer. The NPT  IGBTs, which have equal forward and reverse breakdown voltage, are suitable for AC applications. The PT IGBTs, which have less reverse breakdown voltage than the forward breakdown voltage, are applicable for DC circuits where devices are not required to support voltage in the reverse direction.

Operation Modes

Forward-Blocking and Conduction Modes

When a positive voltage is applied across the collector-to-emitter terminal with gate shorted to emitter the device enters into forward blocking mode with junctions J1 and J3 are forward-biased and junction J2 is reverse-biased. A depletion layer extends on both-sides of junction J2 partly into P-base and N-drift region. An IGBT in the forward-blocking state can be transferred to the forward conducting state by removing the gate-emitter shorting and applying a positive voltage of sufficient level to invert the Si below gate in the P base region. This forms a conducting channel which connects the N+ emitter to the N--drift region. Through this channel, electrons are transported from the N+ emitter to the N--drift. This flow of electrons into the N--drift lowers the potential of the N--drift region whereby the P+ collector/ N--drift becomes forward-biased. Under this forward-biased condition, a high density of minority carrier holes is injected into the N--drift from the P+ collector. When the injected carrier concentration is very much larger the background concentration, a condition defined as a plasma of holes builds up in the N--drift region. This plasma of holes attracts electrons from the emitter contact to maintain local charge neutrality. In this manner, approximately equal excess concentrations of holes and electrons are gathered in the N- drift region. This excess electron and hole concentrations drastically enhance the conductivity of N--drift region. This mechanism in rise in conductivity is referred to as the conductivity modulation of the N--drift region.

Reverse-Blocking Mode

When a negative voltage is applied across the collector-to-emitter terminal, the junction J1 becomes reverse-biased and its depletion layer extends into the N--drift region. The break down voltage during the reverse-blocking is determined by an open-base BJT formed by the P+ collector/ N--drift/P-base regions. The device is prone to punch-through if the N--drift region is very lightly-doped. The desired reverse voltage capability can be obtained by optimizing the resistivity and thickness of the N--drift region.

IGBT

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PIC MICRO CONTROLLERS

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PIC stands for Peripheral Interface Controller given by Microchip Technology to identify its single-chip micro controllers. These devices have been very successful in 8-bit micro controllers. The main reason is that Microchip Technology has continuously upgraded the device architecture and added needed peripherals to the micro controller to suit customers' requirements. The development tools such as assembler and simulator are freely available on the internet at www.electricaltheorems.blogspot.in 

The architectures of various PIC micro controllers can be divided as follows.

Low - end PIC Architectures 

Microchip PIC microcontrollers are available in various types. When PIC microcontroller MCU was first available from General Instruments in early 1980's, the microcontroller consisted of a simple processor executing 12-bit wide instructions with basic I/O functions. These devices are known as low-end architectures. They have limited program memory and are meant for applications requiring simple interface functions and small program & data memories. Some of the low-end device numbers are

12C5XX
16C5X
16C505

Mid range PIC Architectures

Mid range PIC architectures are built by upgrading low-end architectures with more number of peripherals, more number of registers and more data/program memory. Some of the mid-range devices are

16C6X
16C7X
16F87X

Program memory type is indicated by an alphabet.
C = EPROM
F = Flash
RC = Mask ROM

Popularity of the PIC microcontrollers is due to the following factors.

1. Speed: Harvard Architecture, RISC architecture, 1 instruction cycle = 4 clock cycles.
2. Instruction set simplicity: The instruction set consists of just 35 instructions (as opposed to 111 instructions for 8051).
1. Power-on-reset and brown-out reset. Brown-out-reset means when the power supply goes below a specified voltage (say 4V), it causes PIC to reset; hence malfunction is avoided.
   A watch dog timer (user programmable) resets the processor if the software/program ever malfunctions and deviates  from its normal operation.
2. PIC microcontroller has four optional clock sources.
•   Low power crystal
•   Mid range crystal
•   High range crystal
•   RC oscillator (low cost).
3. Programmable timers and on-chip ADC.
4. Up to 12 independent interrupt sources.
5. Powerful output pin control (25 mA (max.) current sourcing capability per pin.)
6. EPROM/OTP/ROM/Flash memory option.
7. I/O port expansion capability.

CPU Architecture

The CPU uses Harvard architecture with separate Program and Variable (data) memory interface. This facilitates instruction fetch and the operation on data/accessing of variables simultaneously.

Fig 1

PIC Memory Organisation

PIC microcontroller has 13 bits of program memory address. Hence it can address up to 8k of program memory. The program counter is 13-bit. PIC 16C6X or 16C7X program memory is 2k or 4k. While addressing 2k of program memory, only 11-  bits are required. Hence two most significant bits of the program counter are ignored. Similarly, while addressing 4k of memory, 12 bits are required. Hence the MSb of the program counter is ignored.

Fig 2

The program memory map of PIC16C74A is shown in Fig 2 
On reset, the program counter is cleared and the program starts at 00H. Here a 'goto' instruction is required that takes the processor to the mainline program.

When a peripheral interrupt, that is enabled, is received, the processor goes to 004H. A suitable branching to the interrupt service routine (ISR) is written at 004H.

Data memory (Register Files)

Data Memory is also known as Register File. Register File consists of two components.

1. General purpose register file (same as RAM).

     2. Special purpose register file (similar to SFR in 8051).

Fig 3

The special purpose register file consists of input/output ports and control registers. Addressing from 00H to FFH requires 8 bits of address. However, the instructions that use direct addressing modes in PIC to address these register files use 7 bits of instruction only. Therefore the register bank select (RP0) bit in the STATUS register is used to select one of the register banks.

In indirect addressing FSR register is used as a pointer to anywhere from 00H to FFH in the data memory.

SLIP RING

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